1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a self-extinguishing type semiconductor device such as a GTO (gate turn-off) thyristor, an SI (static induction) thyristor, and an IGBT (insulated gate bipolar transistor) power transistor, and to a method of manufacturing such a self-extinguishing type semiconductor device.
2. Description of Related Art
A self-extinguishing type semiconductor device such an GTO thyristor, SI thyristor or IGBT has been widely used as a power semiconductor device and has been described in the following documents.
1. Junichi Nishizawa: "High Power Vertical Type Junction FET having Triode Characteristics", Nikkei Electronics, Sep. 27, 1971, pp. 50-61 PA1 2. J. Nishizawa, T. Terasaki and J. Shibata: "Field-Effect Transistor versus Analog Transistor (Static Induction Transistor)", IEEE Trans. on Electron Device, ED-22(4), 185 (1975) PA1 3. J. Nishizawa and K. Nakamura Physiquee Appliquee, T13, 725 (1978) PA1 4. J. Nishizawa and Y. Otsubo: Tech. Dig. 1980 IEDM, 658 (1980) PA1 5. J. Nishizawa, T. Ohmi, T. Sha and K. Mototani: Technological Report of the Electron and Communication Society, ED81-84 (1981) PA1 6. M. Ishidoh, et al: "Advanced High Frequency GTO", Proc. ISPSD, 189 (1988) PA1 7. B. J. Baliga, et al: "The Evolution of Power Device Technology", IEEE Trans. on Electron Device, ED-31, 1570 (1984) PA1 8. M. Amato, et al: "Comparison of Lateral and Vertical DMOS Specific On-resistance", IBDM Tech. Dig., 736 (1985) PA1 9. B. J. Baliga: "Modern Power Device", John Wiley Sons, 350 (1987) PA1 10. H. Mitlehner, et al: "A Novel 8 kV Light-Trigger Thyristor with Over Voltage Self Protection", Proc. ISPSD, 289 (1990)
Among the conventional self-extinguishing type semiconductor devices, the GTO thyristor and SI thyristor are known to have an embedded gate-type structure which can be obtained by forming a gate region in a surface of a semiconductor substrate and then providing an epitaxial layer on that surface. In such GTO thyristors and SI thyristors, since the epitaxial growth has a substrate dependency, the epitaxial layer formed on the surface of the semiconductor substrate, in which the gate region is provided in advance, has such defect that crystal growth on the gate region is different from those on the other portions and a uniform impurity-concentration distribution is not obtained. As a result, it has been difficult to obtain a semiconductor device having good characteristics. In addition, since the epitaxial growth is a relatively time-consuming process, it lowers the throughput of the semiconductor device. Furthermore, there is still another problem that the conductivity type of the epitaxial layer in a vicinity of the gate region is likely to be inverted. To solve these problems, there has been proposed a surface gate-type structure. However, an SI thyristor having the surface gate-type structure cannot have a large reverse voltage and thus, it fails to have a large depletion layer. Accordingly, the SI thyristor with such a structure could not cut off a large current.
When the surface gate-type structure is utilized in a GTO thyristor, there arises a further problem, in addition to those mentioned in the case of SI thyristors, that the gate region cannot have a high impurity-concentration. This results in a low carrier drawing speed and a large turn-off loss and thus, a high frequency property cannot be obtained in the GTO thyristor with this structure.
As a solution for these problems, there has been proposed a serrated gate-type structure. This structure is constituted by forming a groove on a surface of a semiconductor substrate and then providing a gate region in a bottom portion of the groove. However, it is difficult to accurately form a deep groove even by dry etching, and this leads to a poor breakdown voltage. It is also difficult to conduct precise machining in this serrated gate-type structure.
As another solution for the above-mentioned problems, the applicant has proposed, in U.S. patent application No. 08/407,023 now U.S. Pat. No. 5,591,991 as well as corresponding European Patent Application No. 94 921826.7, a method of manufacturing a semiconductor device comprising the steps of forming recesses or depressions in a surface of a first semiconductor substrate of one conductivity type, forming gate regions of the opposite conductivity type at each bottoms of the recesses by introducing impurities from the bottoms of the recesses, providing gate electrodes on the respective gate regions, and joining a second semiconductor substrate to the surface of the first semiconductor substrate. Semiconductor devices having such a joined or contacted structure are free from various problems caused by epitaxial growth. Specifically, in a GTO thyristor, since a gate region can include impurities at a high concentration without any difficulty, the carrier drawing speed can be increased correspondingly and thus, the high frequency property can be attained easily. In an SI thyristor, since gate regions having a high impurity-concentration can be uniformly embedded within a semiconductor substrate, the resulting thyristor has a large gate region area in total. With respect to an IGBT having the contacted structure, the cooling efficiency is greatly improved because the structure enables the IGBT to have a cathode covering the entire surface of a semiconductor substrate. As a result, the IGBT with the joined structure allows a flow of large electric current.
The semiconductor device of the joined structure according to the applicant's proposal, wherein first and second semiconductor substrates are joined to each other, provides various advantages as mentioned above. However, since the joined portion between the two semiconductor substrates has a relatively high electric resistance, the semiconductor device of the joined structure suffers from relatively large electric power consumption and heat dissipation amount. As a solution for such a problem, one may think of forming a high impurity concentration region in the opposite surfaces of the two semiconductor substrates to be joined to each other. However, since a gate structure is formed adjacent to the joined portion, a mere formation of a high impurity concentration region in the joined portion of the substrates forming a gate structure requires masking, etching and impurity diffusion processes, thereby lowering the yield and throughput.
Furthermore, in a cascade-type semiconductor device in which carriers are supplied through the joined portion of the two semiconductor substrates, the joining characteristic of the joined portion plays an important role in manufacturing satisfactory devices. If the two substrates are not properly joined, either an ohmic current-voltage characteristic cannot be obtained, or the joining resistance increases thereby giving rise to increased power lose and heat dissipation amount.